Stefan Rusu

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The next-generation enterprise Xeon ® server processor consists of eight dual-threaded 64b Nehalem cores and a shared L3 cache. The system interface includes two on-chip memory controllers and supports multiple system topologies. Figure 3.1.1 shows the processor block diagram. This design has 2.3B transistors and is implemented in 45nm CMOS using metal-gate(More)
Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm generation and beyond. The first focus area is the process technology, including(More)