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The next-generation enterprise Xeon ® server processor consists of eight dual-threaded 64b Nehalem cores and a shared L3 cache. The system interface includes two on-chip memory controllers and supports multiple system topologies. Figure 3.1.1 shows the processor block diagram. This design has 2.3B transistors and is implemented in 45nm CMOS using metal-gate(More)
—This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon ® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing(More)