Learn More
This paper presents a set of novel metadata extensions that are used to specify the interfaces on Xilinx IP cores and their software models under a uniform data model which allows enhanced design rule checking in the system design process. We also present a suite of tools which can be used to generate executable software simulation models of complete(More)
This paper investigates the cache sizes and configurations that can be supported by a high frequency processor of the next generation. Based on the SIA roadmap prediction that a 0.1u processor of the next generation will run at 3.5GHz, we model caches of that technology using the CACTI tool. Access times as well as energy consumption are modeled for caches(More)
  • 1