Stefan Lachowicz

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(2006). Joint optimization in capacity design of networks with p-cycle using the fundamental cycle set. Abstract— We propose a joint optimization model for capacity design of networks with p-cycles. The model is based on a modified definition of network fundamental cycles and the available straddling links. Concepts about visible and hidden straddling(More)
The paper presents a novel method of evaluating the square root function in FPGA. The method uses a linear approximation subsystem with a reduced size of a look-up table. The reduction in the size of the lookup table is twofold. Firstly, a simple linear approximation subsystem uses the lookup table only for the node points. Secondly, a concept of a variable(More)
The importance of reconfigurable hardware is increasing steadily. For example, the primary approach of using adaptive systems based on programmable gate arrays and configurable routing resources has gone mainstream and high-performance programmable logic devices are rivaling traditional application-specific hardwired integrated circuits. Also, the idea of(More)
The paper presents a novel method of evaluating the square root function in FPGA. The method uses a linear approximation subsystem with a reduced size of a look-up table. The reduction in the size of the lookup table is twofold. Firstly, a simple linear approximation subsystem uses the lookup table only for the node points. Secondly, a concept of a variable(More)
A novel Smart Pixel Opto-VLSI architecture to implement a complete 2-D wavelet transform of real-time captured images is presented. The Smart Pixel architecture enables the realization of a highly parallel, compact, low power device capable of real-time capture, compression, decompression and display of images suitable for Mobile Multimedia Communication(More)
This paper presents a survey of low-power digital Gal-lium Arsenide logic applicable to high performance VLSI circuits and systems and proposes new design concepts in methodology and architecture based on implementation of Pseudo-Dynamic Latched Logic in order to achieve reasonable power-delay-area tradeoff The approach is highly suitable for self-timed(More)