Stefaan Decoutere

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This work analyzes the radio frequency (RF) performance of 60-nm gate length finFETs, for which the DC behavior exhibits reduced SCE. The RF analysis is carried out as a function of the gate length as well as the fin width (W<sub>fin</sub>). Cut off frequencies (f<sub>t</sub>, f <sub>max</sub>) on the order of 100 GHz are reported for the first time. It is(More)
Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them(More)
In this paper, the impact of conventional silicon technology parameters on the characteristics of passives is studied. For both inductors and capacitors, cost-effective modules, which integrate easily into wiring BEOL (back-end of line) in a conventional silicon technology and provide high Q factor components are presented. For an inductor of 3 nH, designed(More)
A novel scheme for deep trench isolation is presented, which uses an airgap as insulator. When incorporated in our 0.13mum SiGe:C BiCMOS technology, the peripheral substrate parasitics decrease with an order of magnitude to a record value of 0.02fF/mum, which significantly improves the device RF performance
The European project DOTFIVE<sup>1</sup> [1] is a 3-year project targeting a 0.5 THz SiGe Heterojunction Bipolar Transistor for the future development of communication, imaging and radar applications. The project proceeds along two paths. It explores further evolutionary scaling of self-aligned selective epitaxial base HBTs, and advanced process modules and(More)
This paper addresses the ESD reliability issues in RFICs, focusing on the technology impact on the device and design. We also present the basic RF ESD protection methods used in industry. Presents the general topology of a 5 GHz LNA, which is protected using several ESD protection methodologies, and describes the 90 nm CMOS process technology used for the(More)