Srinivasa Banna

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Articles you may be interested in Bandgap measurements of low-k porous organosilicate dielectrics using vacuum ultraviolet irradiation Appl. The effect of water uptake on the mechanical properties of low-k organosilicate glass Mechanism of plasma-induced damage to low-k SiOCH films during plasma ashing of organic resists Plasma damage effects on low-k(More)
FinFET geometries have been developed for the sub-22 nm regime to extend Si-CMOS scaling via improved electrostatics compared to planar technology. Moreover, engineers have incorporated high-k oxide gate stacks. Beyond leakage current, less discussed is the impact of the gate oxide's complex band structure on the device performance. However, it defines the(More)
In this work, experimental measurements of the electronic band gap of low-k organosilicate dielectrics will be presented and discussed. The measurement of bandgap energies of organosilicates will be made by examining the onset of inelastic energy loss in core-level atomic spectra using X-ray photoelectron spectroscopy. This energy serves as a reference(More)
More and more high-and low-k dielectrics are used in microfabrication today. However, as is well known, these materials are easily damaged during processing or during operation in a device. Sources of damage include plasma and/or VUV exposure, water uptake, free radicals as well as cosmic rays. A description of the damage effects on dielectrics from water(More)
Conventional 2D CMOS faces severe challenges sub-22nm nodes. The monolithic 3D (M3D) IC technology enables ultra-high density vertical connections and provides a good path for technology node scaling. Transistor-level (TR-L) monolithic 3D IC is the most advanced and fine-grained M3D IC technology. In this paper, for the first time, the detailed design as(More)
In this paper, we develop tier partitioning strategy to mitigate back-end-of-line (BEOL) interconnect delay degradation and cost issues in monolithic 3D ICs (M3D). First, we study the routing overhead and delay degradation caused by tungsten BEOL interconnect in the bottom-tier of M3D. Our study shows that tungsten BEOL reduces performance by up to 30% at(More)
In this paper we study the impact of low thermal budget process on design quality in monolithic 3D ICs (M3D). Specifically, we quantify how much the tier-to-tier transistor performance difference affects full-chip power and performance metrics in a foundry 14nm FinFET technology. Our study first shows that 5%, 10%, and 15% top-tier device degradation in a(More)
With the introduction of FinFET technology in mass production, more designs and complex designs are being ported on 22nm and 14nm/16nm FinFET transistors. However, all FinFET transistors are not made equal to offer best System-on-Chip (SoC) performance and power benefits. Careful selection of fin structural parameters is critical for best SoC performance.(More)
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