Srinivasa Banna

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In this paper, we develop tier partitioning strategy to mitigate back-end-of-line (BEOL) interconnect delay degradation and cost issues in monolithic 3D ICs (M3D). First, we study the routing overhead and delay degradation caused by tungsten BEOL interconnect in the bottom-tier of M3D. Our study shows that tungsten BEOL reduces performance by up to 30% at(More)
In this paper we study the impact of low thermal budget process on design quality in monolithic 3D ICs (M3D). Specifically, we quantify how much the tier-to-tier transistor performance difference affects full-chip power and performance metrics in a foundry 14nm FinFET technology. Our study first shows that 5%, 10%, and 15% top-tier device degradation in a(More)
With the introduction of FinFET technology in mass production, more designs and complex designs are being ported on 22nm and 14nm/16nm FinFET transistors. However, all FinFET transistors are not made equal to offer best System-on-Chip (SoC) performance and power benefits. Careful selection of fin structural parameters is critical for best SoC performance.(More)
FinFET geometries have been developed for the sub-22 nm regime to extend Si-CMOS scaling via improved electrostatics compared to planar technology. Moreover, engineers have incorporated high-k oxide gate stacks. Beyond leakage current, less discussed is the impact of the gate oxide's complex band structure on the device performance. However, it defines the(More)
Conventional 2D CMOS faces severe challenges sub-22nm nodes. The monolithic 3D (M3D) IC technology enables ultra-high density vertical connections and provides a good path for technology node scaling. Transistor-level (TR-L) monolithic 3D IC is the most advanced and fine-grained M3D IC technology. In this paper, for the first time, the detailed design as(More)
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