We present a self-adaptive hierarchical power management technique for massively parallel processor architectures, supporting a new resource-aware parallel computing paradigm called invasive computing. Here, an application can dynamically claim, execute, and release the resources in three phases: resource acquisition (invade), program loading/configuration… (More)
We introduce a novel class of massively parallel processor architectures called invasive Tightly-Coupled Processor Arrays (TCPAs). The presented processor class is a highly parameterizable template which can be tailored before runtime to fulfill costumers' requirements such as performance, area cost, and energy efficiency. These programmable accelerators… (More)
As data locality is a key factor for the acceleration of loop programs on processor arrays, we propose a buffer architecture that can be configured at run-time to select between different schemes for memory access. In addition to traditional address-based memory banks, the buffer architecture can deliver data in a streaming manner to the processing elements… (More)
More functions ‒ multiple standards/modes Higher flexibility More functions in software Higher complexity ‒ algorithmic complexity ‒ image resolutions, etc.
—In this paper, we present an ultra low power design for a class of massively parallel architectures, called tightly-coupled processor arrays. Here, the key idea is to exploit the benefits of a decentralized resource management as inherent to invasive computing for power saving. We propose concepts and studying different architecture trade-offs for… (More)