Srimannarayan Kulkarni

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Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two(More)
In the majority of digital signal processing (DSP) applications the critical operations are the multiplication and accumulation. Real-time signal processing requires high speed and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which is always a key to achieve a high performance digital signal processing system. The purpose of(More)
A low power SRAM memory system is designed and implemented which reduces power consumption both during active and standby modes of operation. This system uses a novel low leak SRAM cell that uses a pair of NMOS and PMOS transistors in the pull down path. The complete memory system is designed to perform write and read operations using this new cell. This(More)
Power dissipation is a bottleneck in the design of low power electronic devices that, operate at high frequencies. Hence, the clock signal is a major source of power dissipation. The technique clock gating at the architecture level can be implemented to reduce the dynamic and clock power. In this paper, the authors aim at implementing, analyzing and(More)
In mobile computing and mobile communication applications powered by battery, the battery life is a premier concern. Leakage power loss is critical in CMOS VLSI circuits as it leaks the battery even when devices are in idle state. To reduce subthreshold leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR(More)
Conventional image partitioning is commonly based on the histogram of the image. It is based on modal distribution and is generally modeled using the mixture of Gaussian distributions. This approach has couple of limitations. Firstly for the Gaussian, if large variance is used, then the partition may include more than one perceivable region. Secondly, if(More)
New Multi-mode SRAM cells to suit applications with different power consumption during both active and sleep mode of states with data preservation requirements are discussed in this work. Proposed PSVG and MNSVP SRAM cells are capable of substantial reduction of leakage power resulting due to subthreshold leakage current and gate leakage current with good(More)
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