Srikanth Jagannathan

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In modern CMOS processes there are numerous failure mechanisms, including soft errors and metastability. Cosmic neutron-induced single event upsets, or soft-errors, have become a dominant failure mechanism in sub-100nm CMOS memory and logic circuits. The effects of metastability have also becoming increasingly significant in high-speed applications(More)
The appropriate choice of flip-flop topologies is of essential importance in the design of integrated circuits for CMOS VLSI high-performance and high-speed circuits. The understanding of the suitability of the flip-flops and select the best topology for a given application is important to meet the need of the design to meet low power and high performance(More)
The synchronizer is constrained such that its state does not change when a latching operation fails. Therefore, any failed latching attempts are automatically retried in the subsequent cycles. For this we simulates the 8 bit multiplier, 4 bit 16 state finite state machine, 16 slot 8 bit data first in first out register etc. In a multi clock system,(More)
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