Sribalan Santhanam

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1 Abstract A reduced instruction set computer (RISC)-style microprocessor has been designed and tested that operates up to 200 megahertz (MHz). The chip implements a new 64-bit architecture, designed to provide a huge linear address space and to be devoid of bottlenecks that would impede highly concurrent implementations. Fully pipelined and capable of(More)
A 300-MHz, custom 64-bit VLSI, second-generation Alpha CPU chip has been developed. The chip was designed in a 0.5-um CMOS technology using four levels of metal. The die size is 16.5 mm by 18.1 mm, contains 9.3 million transistors, operates at 3.3 V, and supports 3.3-V/5.0-V interfaces. Power dissipation is 50 W. It contains an 8-KB instruction cache; an(More)
A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU chip is described. The chip is fabricated in a 0.75-pm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm X 13.9 mm and contains 1.68M transistors. The chip includes separate 8-kilobyte instruction and data caches and a fully pipelined(More)
The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.
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