Spyros Theoharis

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Novel techniques for the power efficient synthesis of sum-of-product computations are presented. Simple and efficient heuristics for scheduling and assignment are described. Different partly static cost functions are proposed to drive the synthesis tasks. The proposed cost functions target the power consumption either in the buses connecting the functional(More)
Our aim is the development of a novel probabilistic method to estimate the power consumption of a combinational circuit under real gate delay model handling temporal, structural and input pattern dependencies. The chosen gate delay model allows handling both the functional and spurious transitions. It is proved that the switching activity evaluation problem(More)
Title: “Generalized Low Power Design Flow” Author(s): N. Zervas, S. Theoharis, D. Soudris, C.E. Goutis, and A. Thanailakis Univerisity of Patras (UP), Democritus University of Thrace (DUTH) Editor: UP Type: Report LPGD Id: LPGD/WP2/UP/D1.3R1 CEC Identifier: EP25256/ UP/D1.3.R1 Document Version: 1 Status: Deliverable Confidentiality: Public Actual Date:(More)