Spiridon Nikolaidis

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— In this paper, a modeling technique for CMOS gates, based on the reduction of each gate to an equivalent inverter, is presented. The proposed method can be incorporated in existing timing simulators in order to improve their accuracy. The conducting and parasitic behavior of parallel and serially connected transistors is accurately analyzed and an(More)
— In this paper a novel energy efficient FPGA architecture was designed and simulated in STM 0.18µm CMOS technology. The parameters of the Configurable Logic Block architecture have been determined in order to minimize energy consumption. Circuit level low power design techniques are also applied for further reducing energy consumption. In addition, an(More)
A novel approach for obtaining the output waveform, the propagation delay and the short-circuit power dissipation of a CMOS inverter is introduced. The output voltage is calculated by solving the circuit differential equation only for the conducting transistor and the effect of the short-circuit current is considered as an additional charge which causes a(More)
– In this paper the measurements taken for the development of instruction-level energy models for microprocessors are presented and analyzed. An appropriate measuring environment and a suitable measuring methodology was developed for taking the necessary measurements. The energy of an instruction is defined as a sum of three components. The pure base energy(More)
A current measurement configuration for the estimation of the power consumption of processing systems is presented in this work. The problem addressed is to measure the variations of the power supply current of digital circuits (and especially of embedded processing circuits) and to calculate from these measurements the energy consumption variations(More)
Energy constraints form an important part of the design specification for processors running embedded applications. For estimating energy dissipation early at the design cycle, accurate power consumption models characterized for the processor are essential. A methodology and the corresponding instrumentation setup for taking current measurements to create(More)
A power consumption measurement framework for embedded processing systems is presented in this work. Given an assembly or machine level program as input to this setup, the energy consumption of the specific program in the specific processing systems may be estimated. The instruction level power models are derived based on the power supply current(More)
SUMMARY A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 µm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box(More)
A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose. According to the proposed method the energy costs (base and(More)
— Modern platform-based design involves the domain-specific extension of embedded processors to fit customer requirements. To accomplish this task, the possibilities offered by recent extensible processors for their instruction set and microarchitectural customization have to be exploited. In this paper, a design approach that encapsulates automated(More)