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To avoid SNR degradation due to jitter, sampling time errors must be less than 90fs rms. This accuracy is achieved through a combination of a low noise clock path and a 2-rank T/H architecture, as shown in Fig. 26.3.1. Clocked at the full 2.5GHz sampling rate via a low-jitter CMOS driver chain, the first T/H stage sets the sampling instant. Eight(More)
The capacitor mismatch in a 1.5-b/stage pipelined ADC is background calibrated in the analog domain using a pseudorandom (PN) dithering concept. The reference voltage added/subtracted during the normal operation is used as a dither to PN-modulate the mismatch error so that it can be embedded into the residue and be recovered later by correlating with the(More)
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