Soumyasanta Laha

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Wireless networks-on-chips (WINoCs) hold substantial promise for enhancing multicore integrated circuit performance, by augmenting conventional wired interconnects. As the number of cores per IC grows, intercore communication requirements will also grow, and WINoCs can be used to both save power and reduce latency. In this article, we briefly describe some(More)
With the increasing number of cores in chip multiprocessors, the design of an efficient communication fabric is essential to satisfy the bandwidth and energy requirements of multi-core systems. Scalable Network-on-Chip (NoC) designs are quickly becoming the standard communication framework to replace bus-based networks. However, the conventional metallic(More)
As both power consumption and leakage currents will limit the scalability of future massively integrated computational systems, research into emerging technologies and devices to replace traditional metallic interconnects has become critical. In this paper we propose an initial implementation for a hybrid wireless network-on-chip (WiNoC) interconnect(More)
With the rise of chip multiprocessors, an energy-efficient communication fabric is required to satisfy the data rate requirements of future multi-core systems. The Network-on-Chip (NoC) paradigm is fast becoming the standard communication infrastructure to provide scalable inter-core communication. However, research has shown that metallic interconnects(More)
There are several 60 GHz transceiver architectures that have been explored and reported in the past employing the On Off Keying (OOK) Modulation. All of these designs are primarily based on the conventional bulk CMOS architecture. In this paper, we propose a power efficient double gate (DG) MOSFET based OOK Transmitter in 32 nm DG FinFET technology. The(More)
This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient (~ 1 pJ/bit) transceivers over extremely short (≤(More)
1.1 CMOS downscaling to DG-MOSFETs As device scaling aggressively continues down to sub-32nm scale, MOSFETs built on Silicon on Insulator (SOI) substrates with ultra-thin channels and precisely engineered source/drain contacts are required to replace conventional bulk devices (Celler & Cristoloveanu, 2009). Such SOI MOSFETs are built on top of an insulation(More)
As energy-efficiency and high-performance of Networks-on-Chips (NoCs) communication fabric have become critical, limited bandwidth and fundamental signaling limitations of metallic interconnects have forced academia and industry to consider emerging technologies such as wireless interconnects as an alternate solution. Wireless interconnects offer multiple(More)
As Network-on-Chip (NoC) architectures become more relevant with an increasing number of cores on a chip, research into emerging technologies and devices to replace power hungry global metallic interconnects has become critical. In this paper, we propose a practical wireless architecture called GLOW, a global wireless interconnect for NoCs. With our(More)