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Design of Vedic IEEE 754 floating point multiplier
- Soumya Havaldar, K. Gurumurthy
- EngineeringIEEE International Conference on Recent Trends in…
- 1 May 2016
A floating point multiplier which manages overflow, underflow and rounding, based on Vedic Urdhva - Tiryagbhyam mathematics is proposed which is proposed to implement faster multipliers involving limited area and consuming reduced power.