Sooryong Lee

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For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective part level can be estimated based upon surrogate detection when test patterns target stuck-at faults in the circuit. For the rst time, test pattern generation techniques that attempt to maximize(More)
Deterministic observation and random excitation of faultsites during the ATPG process dramatically reduces theoverall defective part level. However, multiple observationsof each fault site lead to increased test set size and requiremore tester memory. In this paper, we propose a new ATPGalgorithm to find a near-minimal test pattern set that detectsfaults(More)
Good failure analysis is the ability to determine the site of a circuit defect quickly and accurately. We propose a method for defect site prediction that is based on a site's probability of excitation, making no assumptions about the type of defect being analyzed. We do this by analyzing fault signatures and comparing them to the defect signature. We use(More)
Traditional testing methods attempt to maximize the number of single stuck-at faults detected by the test pattern set applied to minimize defective part level after IC manufacture and prior to shipment. However, stuck-at faults no longer map closely to actual defects in current CMOS technologies. This work optimizes the probability of defect detection-in(More)
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