Sook Min Park

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— Two methods are presented that can substantially reduce the memory requirements of non-binary turbo decoders by efficient representation of the extrinsic information. In the case of the duo-binary turbo decoder employed by the IEEE 802.16e standard, the extrinsic information can be reduced by about 43%, which decreases the total decoder complexity by 18%.(More)
In this paper, VLSI architecture for an efficient turbo decoder with parallel architecture has been studied to achieve high-throughput. For 100% PE utilization, a dividable interleaving method is proposed, which not only solves the memory conflict problem in extrinsic information memory, but also reduces the required memory for interleaver. We mapped the(More)
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