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also provides 3 dBi gain patch antenna and high (50) induc-tors.
— Two methods are presented that can substantially reduce the memory requirements of non-binary turbo decoders by efficient representation of the extrinsic information. In the case of the duo-binary turbo decoder employed by the IEEE 802.16e standard, the extrinsic information can be reduced by about 43%, which decreases the total decoder complexity by 18%.… (More)
In a previous paper (Klapa et al., 1999), we presented a model for the analysis of isotopomer distributions of the TCA cycle intermediates resulting from 13C (or 14C) labeling experiments. Results allow the rigorous determination of the degree of enrichment at specific carbon atoms of metabolites, of the molecular weight distribution of metabolite… (More)
In this paper, VLSI architecture for an efficient turbo decoder with parallel architecture has been studied to achieve high-throughput. For 100% PE utilization, a dividable interleaving method is proposed, which not only solves the memory conflict problem in extrinsic information memory, but also reduces the required memory for interleaver. We mapped the… (More)
Serious BER performance degradation due to finite numeric precision in VLSl implementation of Log-MAP and MAX-Log-MAP decoders where forward state metnc is calculated using reverse tracing method, is analyzed, and two methods are proposed to overcome this problem, the loser storing method for MAX-Log-MAP and the periodic storing method for Log-MAP and… (More)