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Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits
Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks areExpand
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A ultra-low-power FPGA based on monolithically integrated RRAMs
Field Programmable Gate Arrays (FPGAs) rely heavily on complex routing architectures. The routing structures use programmable switches and account for a significant share in the total area, delay andExpand
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A study on buffer distribution for RRAM-based FPGA routing structures
Compared to Application-Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) provide reconfigurablity at the cost of lower performance and higher power consumption. ExploitingExpand
  • 4
Experimental Evaluation of Different Realizations of Recursive CIC Filters
Bit-serial and bit-parallel arithmetic for parallel realization of CIC (cascaded integrator-comb) filters for decimation in DeltaSigma converters are described. This paper goes forward by realizing aExpand
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Design Guidelines for Two-Stage Cascode-Compensated Operational Amplifiers
A new methodology for the design of two-stage cascode-compensated operational amplifiers (opamps) is proposed in this paper. It specifies proper open-loop circuit-level parameters regarding theExpand
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Inter-Plane Communication Methods for 3-D ICs
Three-dimensional (3-D) integration is an emerging candidate for implementing high performance multifunctional systems-on-chip. Employing an efficient medium for data communication among differentExpand
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Design of High-Precision Low-Power Interpolation Modules with Modified SINC Filters
Most high precision sigma delta DACs use SINC filters to provide large stop-band attenuation. They have the highest operating frequency in comparison to other stages and therefore consume most of theExpand
  • 1
Implementation and Synthesis of a Sorting Network
In this paper, we represent sorting algorithm and operation procedure of a sorting network that is a "parallel sorter". This sorter has been programmed by "active-HDL" software and has been examinedExpand
  • 1
Implementation of Multiplier Block with Reduced Adder Cost
The hardware complexity of digital filters (and many other DSP modules) is mainly dominated by the coefficient multipliers. Implementing fixed-point coefficient multiplication as a network of adders,Expand
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