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Journals and Conferences
Soft-decision-based forward error correction (FEC) and its practical implementation for 100 Gb/s transport systems are discussed. In applying soft-decision FEC to a digital coherent transponder, we address the configuration of the frame structure of the FEC. For dual-polarized multilevel modulation formats, the keys are having the FEC frames constructed… (More)
The concatenation of low-density parity-check and Reed-Solomon codes for forward error correction has been experimentally demonstrated for the first time in this letter. Using a 2-bit soft-decision large-scale integration and high-speed field-programmable gate arrays, a net coding gain of 9.0 dB was achieved with 20.5% redundancy with four iterative… (More)
We have developed a 2-bit 32 Gsample/s soft decision LSI for low-density parity-check code FEC at 100 Gb/s in 0.13 mum SiGe-BiCMOS which generates confidence bit with 25 mV<sub>pp</sub> sensitivity.
16-QAM modulation by a single dual-drive Mach-Zehnder modulator with minimum drive voltage employing polar coordinate transformation instead of a vector I/Q modulator was demonstrated. Clear signal separation was observed with 6-bit DAC resolution.
Electronic pre-equalization for 43 Gb/s DQPSK has been demonstrated for the first time. Waveform distortion caused by bandwidth narrowing to 18.1 GHz by cascaded 10 Gb/s ROADMs has been adequately pre-equalized by a SiGe-BiCMOS LSI with 6-bit, 43 GS/s digital-to-analog converters.
We investigated the use of per-channel rate-adaptive FEC for superchannels, in the presence of fiber nonlinearity, inter-channel interference, and power variations. We found 3~4% peak capacity and ~ 0.3dB nonlinear power threshold increase in most cases compared to the conventional method.
Electronic pre-equalization of chromatic dispersion for 43 Gb/s DQPSK has been demonstrated employing a developed test chip. The chip enables the BER in fibre with 2450 ps/nm of dispersion to be improved to 7.6E-05 without an optical dispersion compensator.
We propose to use Han-Kobayashi (HK) coding and dirty-paper coding (DPC) to cope with inter-carrier interference (ICI) in dual-carrier transmissions. We show the considerable benefit of those methods to increase throughput in presence of strong ICI for dense carrier spacing.
The concatenation of LDPC and RS codes has been demonstrated using a real-time FPGA prototype. A net coding gain of 9.0dB for 31.3-Gb/s was achieved with 20.5% redundancy for an input BER of 10<sup>−2</sup>.
We propose a practicable rate-adaptive FEC scheme defeating degradation due to high baud rate and increase of circuit complexity. The preferable coding gains of 13.0-17.5 dB are obtained for 25.5-149.5% redundancies.