Slavisa Jovanovic

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In this paper, we propose a hardware preemptive multitasking mechanism which uses scan-path register structure and allows identifying the total task's register size for the FPGA-based reconfigurable systems. The main objective of this preemptive mechanism is to suspend hardware task having low priority, replace it by high-priority task and restart them at(More)
In this paper, we present a new deadlock-free fault-tolerant adap-tive routing algorithm for the 2D mesh NoC interconnections. The main contribution of this routing algorithm is that it allows both, routing of messages in the networks incorporating the regions not necessarily rectangular, and routing to all nodes which are not completely blocked by faulty(More)
The growing complexity of integrated circuits imposes to the designers to change and direct the traditional bus-based design concepts towards NoC-based. Networks on chip (NoCs) are emerging as a viable solution to the existing interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability.(More)
Networks on chip (NoCs) present viable interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in literature are mostly destined to System-on-chip (SoCs) designs. For a FPGA-based reconfigurable system, the proposed NoCs are not suitable. In this(More)
—Dynamic partial reconfiguration (DPR) of FPGA-based architectures offers a high degree of flexibility and is often an appropriate solution for applications needing dynamically changing contexts. The standard design flow used for design of these architectures still suffer from a lack of adaptability when confronted with applications to implement consisting(More)
  • Hans T J Van Der Steen, Marcel A Groothuis, Jan F Broenink, t T J Vandersteen, M A Groothuis, J F Broenink +8 others
  • 2008
To improve feedback on how concurrent CSP-based programs run, the graphical CSP design tool (gCSP [3,2]) has been extended with animation facilities. The state of processes, constructs, and channel ends are indicated with colours both in the gCSP diagrams and in the composition tree (hierarchical tree showing the structure of the total program).(More)