Slavisa Jovanovic

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In this article, we present CuNoC, a new paradigm for intercommunication between modules dynamically placed on a chip for FPGA-based reconfigurable devices. The CuNoC is based on scalable communication unit called CU which allows the simultaneous communication between several processing elements placed on the chip. We present the basic concept of this(More)
—Adaptive systems based on FPGA architectures can benefit greatly from the high degree of flexibility offered by Dynamic partial reconfiguration (DPR). Thanks to DPR, hardware tasks composing an adaptive system can be allocated and relocated on demand or depending on the dynamically changing environment. The limitations in the existing tools provided by(More)
In this paper, we present a new deadlock-free fault-tolerant adaptive routing algorithm for the 2D mesh NoC interconnections. The main contribution of this routing algorithm is that it allows both, routing of messages in the networks incorporating the regions not necessarily rectangular, and routing to all nodes which are not completely blocked by faulty(More)
In this paper, we propose a hardware preemptive multitasking mechanism which uses scan-path register structure and allows identifying the total task's register size for the FPGA-based reconfigurable systems. The main objective of this preemptive mechanism is to suspend hardware task having low priority, replace it by high-priority task and restart them at(More)
The growing complexity of integrated circuits imposes to the designers to change and direct the traditional bus-based design concepts towards NoC-based. Networks on chip (NoCs) are emerging as a viable solution to the existing interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability.(More)
Networks on chip (NoCs) present viable interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in literature are mostly destined to System-on-chip (SoCs) designs. For a FPGA-based reconfigurable system, the proposed NoCs are not suitable. In this(More)
Network on Chip (NoC) is an approach to designing the communication subsystem between IP cores in a System on a Chip (SoC). NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs. The purpose of NOC is to solve the choke point in communication and the clock problem from architecture. Each route in NOC(More)
—Dynamic partial reconfiguration (DPR) of FPGA-based architectures offers a high degree of flexibility and is often an appropriate solution for applications needing dynamically changing contexts. The standard design flow used for design of these architectures still suffer from a lack of adaptability when confronted with applications to implement consisting(More)