Sizhong Chen

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Signal detector is a key element in a multiple-input multiple-output (MIMO) wireless communication receiver. It has been well demonstrated that nonlinear tree search MIMO detectors can achieve near-optimum detection performance, nevertheless their efficient high-speed VLSI implementations are not trivial. For example, the hardware design of hardor(More)
VLSI implementations of nonlinear MIMO signal detectors are not trivial, particularly for systems with high spectral efficiency. For example, realization of such a detector for 4 times 4 MIMO with 64-QAM still remains missing in open literature. To tackle this challenge, we developed a nonlinear soft-output detector design solution, based on which a(More)
Energy-efficient realization of soft-output signal detection is of great importance in emerging high-speed multiple-input multiple-output (MIMO) wireless communication systems. This paper presents three algorithm-level complexity-reduction techniques for soft-output detector design to achieve significant energy savings. To demonstrate their effectiveness,(More)
This paper presents an implementation-oriented breadthfirst tree search MIMO detector design solution. Techniques at algorithm and VLSI architecture levels are developed to improve the implementation efficiency. Using Synopsys synthesis tool with 0.18μm CMOS technology, we designed soft-output detectors for 4×4 MIMO channel with 64-QAM modulation, which can(More)
Efficient VLSI implementation of multiple-input multipleoutput (MIMO) signal detectors plays an important role in the real-life MIMO communication systems. This paper presents a nonlinear MIMO detector design solution, called relaxed K-best detector, that can support efficient VLSI implementation, while maintaining good detection performance. To the best of(More)
Many pipelined adaptive signal processing systems are subject to a trade-off between throughput and signal processing performance incurred by the pipelined adaptation feedback loops. In the conventional synchronous design regime, such throughput/performance trade-off is typically fixed since the pipeline depth is usually determined in the design phase and(More)
High speed and low power is the dream of circuit designers. In this paper a novel self-timed logic family is presented for high-speed self-timed pipelining applications. We developed a novel triple-rail MOS current mode logic (Tr-MCML) logic family and integrated it seamlessly with self-timed pipelines. This self-timed pipeline is designed to realize(More)
Most pipelined adaptive signal processing systems are inherently subject to a trade-off between throughput and signal processing performance because of the adaptation feedback loops. To mitigate this dilemma, we propose to apply an asynchronous pipeline to implement pipelined adaptive signal processing systems that can support run-time reconfigurable(More)
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