Sivylla E. Paraskevopoulou

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Next generation neural interfaces aspire to achieve real-time multi-channel systems by integrating spike sorting on chip to overcome limitations in communication channel capacity. The feasibility of this approach relies on developing highly efficient algorithms for feature extraction and clustering with the potential of low-power hardware implementation. We(More)
—This paper presents a novel front-end circuit for detecting action potentials in extracellular neural recordings. By implementing a real-time, adaptive algorithm to determine an effective threshold for robustly detecting a spike, the need for calibration and/or external monitoring is eliminated. The input signal is first pre-processed by utilising a(More)
Feature extraction is a critical step in real-time spike sorting after a spike is detected. Features should be informative and noise insensitive for high classification accuracy. This paper describes a new feature extraction method that utilizes a feature denoising filter to improve noise immunity while preserving spike information. Six features were(More)
This work presents a novel unsupervised algorithm for real-time adaptive clustering of neural spike data (spike sorting). The proposed Hierarchical Adaptive Means (HAM) clustering method combines centroid-based clustering with hierarchical cluster connectivity to classify incoming spikes using groups of clusters. It is described how the proposed method can(More)
Problem description The candidate is to develop a ultra-low-power analogue-to-digital converter (ADC) for single channel neuron spike recording using a commercially-available 0.18µm CMOS technology. A key requirement is that the circuit occupies a compact silicon area to allow for scalability within an array. Specically, it is envisaged that the analogue(More)
This paper presents an AC-coupled instrumentation amplifier for electroneurogram (ENG) activity recording. For this design, we evaluate gain and noise requirements based on interference sources (electrodes, power line, EMG). The circuit has been implemented in a commercially-available 0.35μm CMOS technology with total power consumption 460μW. The amplifier(More)
—This paper presents a dynamic front-end towards achieving unsupervised single-neuron activity monitoring. By implementing at the front-end, an automatic gain control that is optimized for neural signal dynamics, subsequent processing can be achieved without the need for calibration. The system uses three amplification stages (low-noise first stage,(More)
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