Sitaram Arkalgud

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The potential for via-mid through-silicon vias (TSVs) can be considerable, since their use allows not only a reduction in interconnect length from several mm to several microns, but also a tremendous increase in bandwidth between the stacked chips. The net result is less power consumption, higher performance, increased device density within a given chip(More)
We compare the influence of different assembly sequences, process parameters and material properties on the resulting package and interposer warpage in 3D stacking configurations. To this end, extensive thermo-mechanical simulations were performed to conduct virtual design of experiments (DOEs) with variables such as substrate and molding material(More)
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