Siraphop Tooprakai

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This paper presents low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is(More)
This paper presents a low-power true single-phase clock 2/3 prescalers at 1.2 V supply voltage. The true single-phase clock divider was developed to help achieve low power and highspeed. All simulation results have been carried out by using Hspice program simulator based on 0.13μm CMOS technology. The power consumption of the proposed circuit is less(More)
Nowadays people widely used mobile phone instead of using landlines phones. This paper proposes to compare the path loss in 850 MHz and 1800 MHz frequency bands by various path loss models. The path loss under terms of the transmitter height and the receiver height. The well known path loss model such as Walfisch-Ikegami (WI), SUI and Ericsson model used to(More)
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