Sing W. Chin

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A 12 bit 50 MSPS pipelined ADC is fabricated in 0.18 mum CMOS process. Internal reference buffers without off-chip capacitors are implemented under 1.8 V power supply voltage for 2 Vp-p input signal swing. Opamp sharing and removal of explicit S/H stage are utilized for low power dissipation. Occupying 1.81times0.76 mm<sup>2</sup>, ADC achieves SNR of 70.4(More)
Abstract: A 14-Bit 2MSample/s pipelined analog-to-digital converter (ADC) has been implemented. High-speed/high-resolution is achieved through the combination of a pipelined ADC architecture with an on-chip 32-bit micro-controller for self-calibration. A low power dissipation of 250mW is achieved on a single 5v supply. Design techniques reduce digital(More)
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