Sina Meraji

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Simulation is perhaps the most cost-effective tool to evaluate the operation of a system under design. A flexible, easy to extend, fully object-oriented, and multilayered simulator for interconnection networks can be a very useful tool for multicomputer designers and researchers. It is so desirable to attach newly designed components to the existing models(More)
The study was undertaken to determine whether the phenomenon of endothelium-dependent relaxation was impaired in the spontaneously diabetic BB Wistar rat. Endothelium-dependent relaxation in the aorta of overtly diabetic animals was compared with that in nondiabetic BB rats. The relaxative responses were elicited in vitro to acetylcholine (-8.0 to -5.5 log(More)
The necklace hypercube has recently been introduced as an attractive alternative to the well-known hypercube. Previous research on this network topology has mainly focused on topological properties, VLSI and algorithmic aspects of this network. Several analytical models have been proposed in the literature for different interconnection networks, as the most(More)
In this paper, we present a dynamic load-balancing algorithm for optimistic gate level simulation making use of a machine learning approach. We first introduce two dynamic load-balancing algorithms oriented towards balancing the computational and communication load respectively in a Time Warp simulator. In addition, we utilize a multi-state Q-learning(More)
As a consequence of Moore’s law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both fast and cost effective. In this paper, we examine the performance of a parallel Verilog simulator(More)
A major part of the design process for Integrated Circuits (IC) is the process of circuit verification, in which the correctness of a circuit's design is evaluated. Discrete event simulation is a central tool in this effort. As proscribed by Moore's law, the number of transistors which can be placed on an IC doubles every 18 months. As a result, simulation(More)
As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. In this paper, we examine the performance of a parallel Verilog simulator on large, real designs. As previous work has made use of either relatively small benchmarks or synthetic(More)
Parallel discrete event simulation can be applied as a fast and cost effective approach for the gate level simulation of current VLSI circuits. In this paper we combine a dynamic load balancing algorithm and a bounded window algorithm for optimistic gate level simulation. The bounded time window prevents the simulation from being too optimistic and from(More)
As proscribed by Moore's law, the size of integrated circuits has grown geometrically, resulting in simulation becoming the major bottleneck in the circuit design process. Parallel simulation provides us with a way to cope with this growth. In this paper, we describe an optimistic (time warp) parallel discrete event simulator which can simulate all(More)
In this paper, we show how we use Nvidia GPUs and host CPU cores for faster query processing in a DB2 database using BLU Acceleration (DB2's column store technology). Moreover, we show the benefits and problems of using hardware accelerators (more specifically GPUs) in a real commercial Relational Database Management System(RDBMS).We investigate the effect(More)