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Formal languages are increasingly used to describe the functional requirements (specifications) of circuits. These requirements are used as a means to communicate design intent and as basis for verification. In both settings it is of utmost importance that the specifications are of high quality. However, formal requirements are seldom the object of… (More)
The IEEE standard property specification language (PSL) allows to express all omega-regular properties mixing linear temporal logic (LTL) with sequential extended regular expressions (SEREs), and is increasingly used in many phases of the hardware design cycle, from specification to verification. Many verification engines are able to manipulate… (More)
The DEGAS project aims at enriching standard UML-centred development environments in such a way that the developers of global applications can exploit automated formal analyses with minimal overhead. In this paper, we present For-LySa, an instantiation of the DEGAS approach for authentication analysis, which exploits an existing analysis tool developed for… (More)
PU Public PP Restricted to other programme participants (including the Commission Services) RE Restricted to a group specified by the consortium (including the Commission Services) CO Confidential, only for members of the consortium (including the Commission Services) This document is intended to fulfill the obligations of the PROSYD project concerning… (More)
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