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Polynomial evaluation is important across a wide range of application domains, so significant work has been done on accelerating its computation. The conventional algorithm, referred to as Horner's rule, involves the least number of steps but can lead to increased latency due to serial computation. Parallel evaluation algorithms such as Estrin's method have(More)
This paper presents an optimised high throughput architecture for integer squaring on FPGAs. The approach reduces the number of DSP blocks required compared to a standard multiplier. Previous work has proposed the tiling method for double precision squaring, using the least number of DSP blocks so far. However that approach incurs a large overhead in terms(More)
In order to improve the effectiveness and speed of edge detection, an improved Canny operator is introduced in this paper for PCB wire edge detection. By adopting an adaptive scale Gaussian filter on the input PCB image, we remove white noise while preserving edge information. For the shortcomings of the traditional Canny operator on slow Gaussian(More)
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