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This paper proposes a double edge-triggered half­ static clock-gated D-type flip-flop (DHSCGFF), which consists of two parallel dynamic master latches connected in parallel and a single half-static latch with clock-gating circuit. The proposed DHSCGFF makes use of a clock-gating circuit to achieve better race tolerance, circuit compactness and energy(More)
This paper enumerates high speed design of RS & D-flip-flop using AlGaAs/GaAs MODFET. The proposed Flip Flop is having less number of transistors than existing designs. Simulation results show lowest average power and least delay than existing designs. This Flip-Flop having less number of transistors. It can be efficiently used in VLSI ICs. In the(More)
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