Siavash Bayat Sarmadi

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Cryptographic systems implemented using VLSI technologies require a large number of circuits and are prone to various types of faults. Attacks on cryptosystems that exploit erroneous results due to deliberately injected faults in hardware have recently been reported in the literature. As a result, the detection and the correction of errors in cryptographic(More)
In this article we consider detection of errors in polynomial basis multipliers, which have applications in channel coding, VLSI testing, and cryptography. Error detection is performed by applying a class of linear codes while the multiplier is in use. In this article, two error detection schemes are presented. Results show that the probability of error(More)
—Hardware trojan horses (HTH) have recently emerged as a major security threat for field-programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs may still leave a considerable amount of logic resources to be misused by malicious attacks. This letter presents a low-level HTH protection scheme for FPGAs by filling the unused resources(More)
Most lattice-based cryptographic schemes with a security proof suffer from large key sizes and heavy computations. This is also true for the simpler case of authentication protocols that are used on smart cards as a very-constrained computing environment. Recent progress on ideal lattices has significantly improved the efficiency and made it possible to(More)
In this work we consider mainly detection of errors in polynomial, dual and normal bases arithmetic operations. Error detection is performed by recomputing with shifted operands method while the operation unit is in use. This scheme is efficient for pipelined architectures, particularly systolic arrays. Additionally, One semi-systolic multiplier for each of(More)
This paper investigates the concurrent detection of multiple-bit errors in polynomial basis (PB) multipliers over binary extension fields. To this end, multiple parity bits are considered for both inputs of the multiplier. For the multiplier architecture considered here, the two inputs go through considerably different sets of circuits and this allows us to(More)