Siamak Modjtahedi

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This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the(More)
This paper presents a transceiver that uses a 4-bit flash ADC for the receiver and an 8-bit current-steering DAC for the transmitter. The 8-GSa/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the accuracy of the interleaved sampling clocks to within 10 ps, and(More)
This 8GSymbol/s equalized transceiver is based on time-interleaved DACs and ADCs. The symbol time of 1 fanout-of-4 (FO-4) gate delay matches the speed of the fastest binary transceivers [2], while the ADCs and DACs support digital communication techniques to overcome wire losses, interference, and impedance discontinuities. The limitations of the relatively(More)
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