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Implementation of a third-generation 1.1GHz 64b microprocessor
TLDR
This third-generation 1.1-GHz 64-bit UltraSPARC microprocessor provides 1-MB on-chip level-2 cache, 4-Gb/s off chip memory bandwidth, and a new 200 MHz JBus interface that supports one to four processors. Expand
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A power effective 5-bit 600 MS/s binary-search ADC with simplified switching
TLDR
This paper proposes the design of a binary search ADC that uses two different techniques, namely, distributed-residue and folding. Expand
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A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC
TLDR
A 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC architecture is proposed, where the ADC's front-end is built with a 5b binary search ADC, shared by two time-Interleaved 6b SAR ADCs in the 2nd-stage. Expand
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Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC
TLDR
This brief reports a 120 MS/s 12-bit successive approximation register analog-to-digital converter that improves both the dynamic performance and the static performance of the ADC. Expand
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A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC
TLDR
A 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC architecture is proposed, where the ADC's front-end is built with a 5b binary search ADC, shared by two time-Interleaved 6b SAR ADCs in the 2nd-stage. Expand
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Parasitic calibration by two-step ratio approaching technique for split capacitor array SAR ADCs
TLDR
A calibration technique is proposed to apply for split capacitor array of successive approximation register (SAR) ADC, with 15% to 25% of top plate parasitic capacitance. Expand
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A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators
TLDR
This paper presents a topology to improve the system linearity and reduce the complexity of high-speed binary-search ADCs. Expand
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Comparator-based successive folding ADC
TLDR
A 4-bit 1-GS/s ADC with a comparator-based successive folding (CSF) architecture is presented to enhance quantization speed and achieve less complexity, leading to high power efficiency. Expand
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