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Design issues and insights of multilevel phase change memory are presented. Based on a proposed compact model calibrated to measured data, we assess the impact of resistance drift on multilevel cell design. It is found that special care has to be taken to develop a viable multilevel design as the design window could be degraded and worsened at high(More)
The use of low voltage circuits and power-off mode help to reduce the power consumption of chips. Non-volatile logic (nvLogic) and nonvolatile SRAM (nvSRAM) enable a chip to preserve its key local states and data, while providing faster power-on/off speeds than those available with conventional two-macro schemes. Resistive memory (memristor) devices feature(More)