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Continuous ongoing development of dense integrated circuits requires significant advancements in nanoscale patterning technology. As a key process in semiconductor high volume manufacturing (HVM), high resolution lithography is crucial in keeping with Moore's law. Currently, lithography technology for the sub-7 nm node and beyond has been actively(More)
In advanced technology nodes, the BEOL requires advanced patterning techniques such as triple patterning (LELELE) and side wall image transfer techniques to form metal and via structures with pitches below 50nm. In this paper, we demonstrate metal critical dimension (CD) shrinkage using atomic layer deposition (ALD) enabled spacer layer to achieve sub-50 nm(More)
10nm M1 local interconnect is using three-color litho-etch-litho-etch-litho-etch (LELELE) integration to enable technology scaling. This paper discusses the challenges to balance the three-color density in critical standard cell scaling, illustrates the limited process margin resulting from iso-dense loading during dry etch CD shrink, and proposes a novel(More)
The rapid development in dense integrated circuits requires significant advancement in small scaling patterning technology. EUV technology is considered as a powerful solution for the sub-7 nm node pattering and beyond. The high performance resist development is required for the practical applications of the EUV patterning for high volume manufacturing. In(More)
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