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Journals and Conferences
A post-packaging auto repair technique is implemented in a 36Mb embedded DRAM macro of 6ns cycle time. It consists of internal compare circuit, redundancy analyzer, and anti-fuses. The internal auto programming of anti-fuse fixes post-packaging failures.
A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated… (More)
A ferroelectric capacitor overdrive technique with shield-bitline drive has been demonstrated and verified by a 130 nm 576 Kb test chip with a 0.7191 m cell. First, cell signal degradation and bitline-to-bitline coupling noise worsened by wide cell signal distribution in low voltage scaled FeRAMs are discussed. Next, the shield-bitline-overdrive technique… (More)