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Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform
TLDR
This brief presents an improved task partitioning of the Montgomery multiplication algorithm for the multicore platform with area-efficient processors to verify the efficiency of parallelization.
Configurable Pipelined Gabor Filter implementation for fingerprint image enhancement
TLDR
A novel Gabor filter hardware scheme for the fingerprint image enhancement is presented that uses accurate local frequency and orientation to generate the corresponding convolution kernel and thus achieve a better enhancement effect.
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation
TLDR
The proposed multicore processor provides flexible and efficient computation for various forms of RSA and ECC algorithms, fulfilling low-latency or high-throughput requirements of different application scenarios, by using a heterogeneous multicore architecture.
An 800Mhz cryptographic pairing processor in 65nm CMOS
TLDR
This paper presents a high-performance pairing processor with a new combined Montgomery multiplier which implements the fundamental operations of Fp2 multiplication efficiently.
A low-complexity heterogeneous multi-core platform for security soc
TLDR
Comparison results shows that this heterogeneous multi-core SoC platform to deal with intensive cryptography algorithms in different security protocols also has a low-complexity hardware cost but more flexibility.
A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms
TLDR
A quad-core processor that accelerates public-key computations by enabling high-speed parallel task processing and is superior to the powerful platforms like Nvidia GPU and AMD Opteron workstation.
The design and implement of a mobile security SoC
TLDR
A MIPS-like general processor, a dedicated package processor for fast data package, and multiple security processors for cryptography are integrated in the SoC and the performance can be greatly enhanced by the well-designed DTU (Data Transfer Unit), memory architecture and synchronization units.
A security processor based on MIPS 4KE architecture
TLDR
A security processor based on MIPS 4KE architecture which extends security functions of AES and ECC, which is compatible to the leading software development tools of industry and verified by an experimental chip.
A NoC-based multi-core architecture for IEEE 802.11i CCMP
TLDR
A heterogeneous multi-core architecture based on NoC to support high-speed CCMP application and achieves a throughput of 787Mbps at 84MHz is presented.
Analysis of adaptive support-weight based stereo matching for hardware realization
TLDR
The proposed SWWR technique can shorten computation time by the number of disparities, and Left-Right Cost Reuse to achieve bandwidth reduction by more than half, and the comparison states that the proposed flow can generate much better disparity results, and meets the real-time constraint with relatively low memory cost and bandwidth.