Shruti Padmanabha

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Heterogeneous multicore systems -- comprised of multiple cores with varying capabilities, performance, and energy characteristics --have emerged as a promising approach to increasing energy efficiency. Such systems reduce energy consumption by identifying phase changes in an application and migrating execution to the most efficient core that meets its(More)
Experiments reported previously demonstrate that freeflying honeybees are able to detect static intensity fluctuations as weak as 26 nT against the background, earth-strength magnetic field. We report here an extension of this work to weak, alternating fields at frequencies of 10 and 60 Hz. Our results indicate that the sensitivity of the honeybee(More)
Heterogeneous multicore systems are composed of multiple cores with varying energy and performance characteristics. A controller dynamically detects phase changes in applications and migrates execution onto the most efficient core that meets the performance requirements. In this paper, we show that existing techniques that react to performance changes break(More)
Heterogeneous multicore systems—comprising multiple cores with varying performance and energy characteristics—have emerged as a promising approach to increasing energy efficiency. Such systems reduce energy consumption by identifying application phases and migrating execution to the most efficient core that meets performance requirements. However, the(More)
Heterogeneous architectures offer many potential avenues for improving energy efficiency in today's low-power cores. Two common approaches are dynamic voltage/frequency scaling (DVFS) and heterogeneous microarchitectures (HMs). Traditionally both approaches have incurred large switching overheads, which limit their applicability to coarse-grain program(More)
InOrder (InO) cores achieve limited performance because their inability to dynamically reorder instructions prevents them from exploiting Instruction-Level-Parallelism. Conversely, Out-of-Order (OoO) cores achieve high performance by aggressively speculating past stalled instructions and creating highly optimized issue schedules. It has been observed that(More)
Heterogenous chip multiprocessors (Het-CMPs) offer a combination of large Out-of-Order (<i>OoO</i>) cores optimized for high single-threaded performance and small In-Order (<i>InO</i>) cores optimized for low-energy and area costs. Due to practical constraints, CMP designers must choose to either optimize for total system throughput by utilizing many(More)
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