complex data memory. The validity and efficiency of the architecture have been verified by simulation in hardware description language VHDL.
Design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the r a d i ~-2 ~ algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in PLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data… (More)
A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-2' algorithm is derived by integrating a twiddle factor decomposition technique in the divide and conquer approach. R a d i ~-2 ~ algorithm has the same multiplicative complexity as radix-4 algorithm, but retains the butterfly structure of radix-2 algorithm.… (More)