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Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elasticization is one approach (among others) of transforming an ordinary clocked circuit into a latency insensitive design. This paper presents practical considerations of elasticizing(More)
The System-on-Chip era has arrived, and it arrived quickly. Modular composition of components through a shared interconnect is now becoming the standard, rather than the exotic. Asynchronous interconnect fabrics and globally asynchronous locally synchronous (GALS) design has been shown to be potentially advantageous. However, the arduous road to developing(More)
Asynchronous handshake protocol communication is accomplished by sending data down a communication link coupled with data validity information. Flow control is established by acknowledging the receipt of data, thereby enabling transmission of new data down the link. Handshake protocols operate at target cycle times based on system operational requirements.(More)
The eminence of communication costs over computation costs in current systems-on-chip (SoCs) has led to a change in the assumptions and methodology of the deep submicron design process. The emergence of non-traditional global signaling techniques such as optical interconnects, wireless communication, and transmission lines adds further complexity to the(More)
Implementation of low energy, low latency transmission line interconnects on a network-on-chip presents the circuit designer with a variety of structural design choices. This work presents a study of the comparative effects of changing the wire geometries on the latency, energy dissipated, area, and noise properties of the transmission lines. These results(More)
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