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- Shmuel Wimer, Israel Koren
- IEEE Trans. VLSI Syst.
- 2012

Gating of the clock signal in VLSI chips is nowadays a mainstream design methodology for reducing switching power consumption. In this paper we develop a probabilistic model of the clock gating network that allows us to quantify the expected power savings and the implied overhead. Expressions for the power savings in a gated clock tree are presented and the… (More)

- Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer
- 2011 14th Euromicro Conference on Digital System…
- 2011

As the number of applications and programmable units in CMPs and MPSoCs increases, the Network-on-Chip (NoC) encounters unpredictable, heterogeneous and time dependent traffic loads. This motivates the introduction of adaptive routing mechanisms that balance the NoC's loads and achieve higher throughput compared with traditional oblivious routing schemes.… (More)

- Reuven Bar-Yehuda, Jack A. Feldman, Ron Y. Pinter, Shmuel Wimer
- IEEE Trans. on CAD of Integrated Circuits and…
- 1989

Abstruct-We describe a new algorithmic framework for mapping CMOS circuit diagrams into area-efficient, high-performance layouts in the style of one-dimensional transistor arrays. Using efficient search techniques and accurate evaluation methods, the huge solution space that is typical to such problems is traversed extremely fast, yielding designs of… (More)

- Shmuel Wimer, Israel Koren
- IEEE Trans. on CAD of Integrated Circuits and…
- 1988

- Shmuel Wimer, Israel Koren, Israel Cederbaum
- DAC
- 1988

The building blocks in a given floorplan may have several possible physical implementations yielding different layouts. This paper discusses the problem of selecting an optimal implementation for each building block so that the area of the final layout is minimized. A polynomial algorithm that solves this problem for slicing floorplans was presented… (More)

- Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman
- IEEE Transactions on Computer-Aided Design of…
- 1987

We describe an algorithm that maps a CMOS circuit diagram into an area-efficient, high-performance layout in the style of a transistor chain. It is superior to other published algorithms of this kind in terms of the class of input circuits it accepts, its efficiency, and the quality of the results it produces. This algorithm is intended for the automatic… (More)

- Shmuel Wimer, Israel Koren
- IEEE Trans. VLSI Syst.
- 2014

Clock gating is a predominant technique used for power saving. It is observed that the commonly used synthesisbased gating still leaves a large amount of redundant clock pulses. Data-driven gating aims to disable these. To reduce the hardware overhead involved, flip-flops (FFs) are grouped so that they share a common clock enabling signal. The question of… (More)

- Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
- ACM Trans. Design Autom. Electr. Syst.
- 2009

The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted Power-Delay Sum (WPDS) objective function and derive necessary and sufficient conditions for the existence of optimal interwire space… (More)

- Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
- Integration
- 2015

Reduction of interconnect delay and interconnect power has become a primary design challenge in recent CMOS technology generations. Spacing between wires can be modified so that line-to-line capacitances will be optimized for minimal power under timing constraints. In this paper, we present a novel algorithm for simultaneous multilayer interconnect spacing… (More)

- Shmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny
- IEEE Trans. on Circuits and Systems
- 2006

The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor to next generation technology. In this paper, timing… (More)