Shiva Navab

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In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same number of switches and buses as the standard reconfigurable meshes, is capable of simultaneously transmitting N waves on each of the spin-wave buses. Because of this highly parallel(More)
1 The authors are listed alphabetically by last name. Abstract In this paper, we show how to form Partial-Order Multiple-Sequence Alignment graphs on two types of reconfigurable mesh architectures. The first reconfigurable mesh is a standard micro-scale one that uses electrical interconnects, while the second one can be implemented at a nano-scale level and(More)
In this article, we present a nanoscale reconfigurable mesh which is interconnected by ferromagnetic spin-wave buses. In this architecture, unlike the traditional spin-based nano structures which transmit charge, waves are transmitted. As a result, the power consumption of the proposed modules can be low. This reconfigurable mesh, while requiring the same(More)
1 The authors are listed in alphabetical order. Abstract In this paper, we present three hierarchical multi-scale architectures that are interconnected electro-optically at micro-scale level and via spin waves at nano-scale level. These architectures are derived from the Optical Reconfigurable Mesh (ORM), which is a MEMS architecture that supports several(More)
In this paper, we present a number of parallel and fault-tolerant routing schemes for a set of nanoscale spin-wave architectures. The architectures considered here have several features, including the ability to simultaneously transmit multiple data on the same spin-wave bus using different frequencies, as well as the capability to perform concurrent(More)
In this paper, we study the algorithm design aspects of three newly developed spin-wave architectures. The architectures are capable of simultaneously transmitting multiple signals using different frequencies, and allow for concurrent read/write operations. Using such features, we introduce a set of generic parallel processing techniques that can be used(More)