Shiro Kamohara

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A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14μA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias-Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.
We propose a general method for repair-yield estimation based on critical area analysis using a commercial Monte-Carlo simulator. We classify failures into several types according to the repair rules and use iterative critical area analysis for each type of failure (ICAA-ETF) to calculate the repair yield. Our proposed method makes it possible to accurately(More)
Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power(More)
We propose a circuit performance oriented device optimization methodology using pre-silicon parameters and critical paths which represent the performance of the chip. Based on our methodology, we successfully reduced the power consumption by 90% and, at the same time, increased the frequency by 30% from the initial design. The key to this optimization(More)
Statistical distributions of four write stability metrics at low supply voltage (V<sub>DD</sub>) were measured in 1k fully depleted (FD) silicon-on-thin-BOX (SOTB) and bulk SRAM cells. It is found that butterfly curve shows abnormal &#x201C;two-mode&#x201D; distributions, while bit-line and word-line margins maintain good normality even at low(More)
A 32bit CPU, which can operate more than 100 years with 610mAH Li battery, or eternally operate with an energy harvester of in-door light is presented. The CPU was fabricated by using 65nm SOTB CMOS technology (Silicon On Thin Buried oxide) where gate length is 60nm and box layer thickness is 10nm. The threshold voltage was designed to be as low as 0.19V so(More)