Shing I. Kong

Learn More
The dynamic instruction counts of MIPS and SPARC are compared using the SPEC benchmarks. MIPS typically executes more user-level instructions than SPARC. This difference can be accounted for by architectural differences, compiler differences, and library differences. The most significant differences are that SPARC’S double-precision floating point(More)
As computer system main memories get larger and processor cycles-per-instruction (CPIs) get smaller, the time spent in handling translation lookaside buffer (TLB) misses could become a performance bottleneck. We explore relieving this bottleneck by (a) increasing the page size and (b) supporting two page sizes. We discuss how to build a TLB to support two(More)
  • 1