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In sub-100-nm processes, many physical phenomena have become critical issues in the development of processes, devices, and circuits. To achieve reasonable compromise in ASIC design, device-and process-level characterization of physical designs is a fundamental requirement. In this paper, we address topics regarding "design for variability", which are(More)
SUMMARY We propose guidelines for LSI-chip design, taking the within-die variations into consideration, and for process quality improvement to suppress the variations. The auto-correlation length, λ, of device variation is shown to be a useful measure to treat the systematic variations in a chip. We may neglect the systematic variation in chips within the(More)
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