Shin-ichi Ohkawa

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In sub-100-nm processes, many physical phenomena have become critical issues in the development of processes, devices, and circuits. To achieve reasonable compromise in ASIC design, device-and process-level characterization of physical designs is a fundamental requirement. In this paper, we address topics regarding "design for variability", which are(More)
In sub-100nm processes, various physical phenomena come up as critical red-brick in designing circuits and LSIs. We focus on design for variability (DFV) for LSI-chip design, taking the within-die variations into consideration. Main approach for the purpose is a new Test Structure (TEG: Test Element Group) to measure the within-die variation of elements(More)
We propose guidelines for LSI-chip design, taking the within-die variations into consideration, and for process quality improvement to suppress the variations. The auto-correlation length, λ, of device variation is shown to be a useful measure to treat the systematic variations in a chip. We may neglect the systematic variation in chips within the range of(More)
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