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We propose a 6-bit 2.5Gsample/s flash-ADC realized in a digital 0.18um 1-Poly 4-Metal CMOS technology. To achieve low power with wide analog bandwidth and good performance, we employ active interpolation and new comparator latch scheme. The simulation results show that the implemented A/D converter has an effective number of bits (ENOB) of 5.99bit at 224MHz(More)
This paper describes some design techniques for high speed and low power pipelined 8-bit 250MSPS ADC. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. To reduce the power consumption and the die area, the number of(More)
Abstract In this paper, a 4-bit 1.356GS/s analog to digital (A/D) converter using current pre-processing (CMA, DSA) is presented. To achieve low power consumption and high conversion rate, the proposed converter is designed with current mode amplifier (CMA) and each preamplifier includes a dual sense amplifier (DSA). The A/D converter can sample input(More)
This paper presents a new skew control technique for a high speed mobile display serial interface. Unstable frequency and distorted duty ratio of recovered clock from the skew of data and strobe can be adjusted simultaneously by the proposed adaptive strobe delay controller (ASDC). Clock regulation is important because a raster image is re-constructed by(More)