Shih-Hsien Lo

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Power management has become a key constraint in the design of modern digital VLSI chips. Moreover, with minimum transistor dimensions reaching 100-nm and below, traditional scaling has slowed down. The ITRS roadmap has indicated that device mobility enhancement would be necessary to maintain the generational performance improvement in the sub-100nm VLSI(More)
Several novel schemes of implementing MTCMOS circuits in hybrid UTSOI-epitaxial CMOS structures are proposed and analyzed through comprehensive circuit simulations. The schemes offer intrinsic high circuit density and facilitate header/footer body biasing techniques for performance enhancement and leakage reduction. The effectiveness in improving(More)
Double Gate (DG) FETs have emerged as the most promising technology for sub-50nm transistor design. However, analysis and control of the gate tunneling leakage in DGFET is necessary to fully exploit their advantages. In this paper we have modeled (numerically and analytically) and analyzed gate-to-channel leakage in different DGFET structures, namely, doped(More)
Double gate (DG) FETs have emerged as the most promising technology for sub-50 nm transistor design. However, analysis and control of the gate tunneling leakage in DGFET is necessary to fully exploit their advantages. In this paper we have modeled (numerically and analytically) and analyzed gate-to-channel leakage in different DGFET structures, viz., doped(More)
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