Shigeto Tanaka

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This paper reports the first low (1.5 V) supply voltage D-F/F able to run at a full rate of over 43 Gb/s. The proposed F/F circuitry incorporates parallel current switching together with inductive peaking, a combination that makes it suitable for over-43-Gb/s operation at a supply voltage as low as 1.5 V. The D-F/F, implemented through an InP-HBT process,(More)
PURPOSE To elucidate Japanese trends for perioperative disinfection and antibiotic selection during cataract surgeries. METHODS Perioperative iodine use and antibiotic prophylaxis for cataract surgery were surveyed in eight regions in Japan by mail or through interviews from February 1 to March 1, 2014. RESULTS We surveyed 572 surgeons, of whom 386(More)
This paper presents a new single PLL and single SSB-mixer architecture for a local signal generator of the Mode-1 MB-OFDM UWB systems. Using a VCO running at 8976 MHz and a divide-by-2 circuit, it can provide a 4488-MHz carrier signal with low-spurious levels, which is required to meet the spectrum mask requirements being considered in Japan and Europe. A(More)
We have developed a power-gating technique for a mobile processor in 28-nm HKMG technology. The proposed EM-tolerant 1.8V I/O NMOS power switch reduces the standby power to 1/641× and achieves 79% channel utilization without weakening EM immunity. The active leakage power of the dual CPU cores can be reduced by 45 mW in a single core operation mode(More)
SUMMARY This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (AD) converted without correcting errors, but by exchanging(More)
SUMMARY The possibility of realizing a CMOS pipelined current-mode AD converter (ADC) for video applications has been examined. Two times the input current is obtained at the output of a bit-block of a pipelined ADC by subtracting the negative output current from the positive output current in the pseudo-differential configuration. Subtraction of the(More)
— This paper proposes a simple method to realize an over-sampling pipelined analog-to-digital converter (ADC) with 1.5-bit bit-blocks. The ADC performs conversion by permuting internal capacitors in alternate clocks of the upper 1.5-bit bit-blocks in the analog domain, then averaging the data from bit-blocks in the digital domain. The behavioral simulation(More)
A 3.6-watt 26-GHz band AlGaAs/GaAs heterojunction bipolar transistor (HBT) power amplifier is described. The amplifier is composed of two common-base (CB) HBT chips, and achieves a output power of 3.63 W (35.6 dBm), power-added efficiency (PAE) of 21.2% and associated gain of 6.2 dB with a 1-dB bandwidth between 25.5 and 26.5 GHz. As far as we know, the(More)
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