Shigeto Maegawa

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In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (VDD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage(More)
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated on 130nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100ms at 80/spl deg/C. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional(More)
This paper describes the experimental characteristics of RF components with layout and structural optimization, fabricated in 0.10-mum 1.2-V SOI-CMOS technology with partial trench isolation (PTI). ESD protection-grounded gate SOI-NMOSFETs achieve high reliability due to body-tied structure with PTI, and newly proposed ESD diodes also derive superior(More)
This paper discusses Mixed Signal LSI technology with embedded power transistors. Trends in Mixed Signal LSI technology are explained at first. Mixed signal LSI technology has proceeded with the help of fine fabrication technology and SOI technology. The BEOL transistor is a new development, which uses InGaZnO (IGZO) as its TFT channel material. The BEOL(More)
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