Shidhartha Das

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Abstract In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18μm technology . The processor employs a delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst(More)
Traditional adaptive methods that compensate for PVT variations need safety margins and cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors. Error detection is based on flagging spurious transitions in(More)
Razor is a hybrid technique for dynamic detection and correction of timing errors. A combination of error detecting circuits and micro-architectural recovery mechanisms creates a system that is robust in the face of timing errors, and can be tuned to an efficient operating point by dynamically eliminating unused timing margins. Savings from margin(More)
signal which overwrites the shadow latch data into the errant flipIn this paper, we present the implementation and silicon flop. A distributed pipeline recovery mechanism [1] is implemented measurements results of a 64bit processor fabricated in 0. 18ptm to recover correct pipeline state (figure lb). The minimum allowed technology. The processor employs a(More)
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for poweraware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale(More)
We review adaptive design techniques with particular emphasis on error-tolerant techniques. We compare and contrast traditional adaptive approaches with error-tolerant techniques and analyze the margins eliminated by each of them. We discuss the applications of the latter to on-chip communication and signal-processing. Finally, we focus on a specific(More)
Efficient Data Center Architectures Using Non-Volatile Memory and Reliability Techniques by David Andrew Roberts Chair: Trevor N. Mudge The cost of running a data center is increasingly dominated by energy consumption, contributed by power provisioning, cooling and server components such as processors, memories and disk drives. Meanwhile, emerging classes(More)
In this paper, we present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency of digital signal processing datapaths without loss of robustness. Timing errors are detected using razor flip-flops on critical-paths, and the error-rate feedback is used to control a dynamic voltage scaling control loop. In place of(More)