Shi Jiangang

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In this paper, a low power, high density and fully integrated CMOS receiver front-end with digital output for optical signal processing systems is presented. The circuit is composed of transimpedance amplifier for weak optical current detection, limiting amplifier for both linear and limiting amplifications, control circuits and the digital output(More)
In this study, the digital static calibration technique used for 400MSPS, 16-bit high-resolution current steering DAC is described. The technique uses address generator, comparator, SAR register, and calibration DAC to comprise successive approximation calibration loop. With the calibration loop, the respective calibration of array units of current source(More)
A proposed under-voltage lockout of compensated temperature coefficient threshold voltage without comparator is presented in this paper. The circuit achieves stability of threshold voltage without utilizing extra band gap reference voltage source and voltage comparator. In the temperature range of from -40°C to +125°C, variation of only 30mV of the(More)
As a new model of enterprises business cooperation, fair and reasonable mechanism of profit allocation relates to the success or fair of the supply chain alliance. This paper applied symbiosis theory and conception into supply chain alliance which is a man-made symbiotic system, combined with Material and Energy Transformation Law, Quality Action Law,(More)
ESD failure of an operational amplifier in submicron CMOS technology is analyzed to locate the failure mechanism and re-design the protection structure in this paper. From the experimental results, the specifications related to the output stage with large size devices are degraded or exceed the qualified range. With the deep analysis of internal circuit of(More)
An input stage using Darlington configuration with a lateral PNP and a vertical PNP combination for operational amplifier (Op-Amp) is presented in this paper. The emitter degeneration resistors are added to enhance the slew rate of the amplifier. To decrease the input offset voltage, the base current traced compensation technique is used to balance and(More)
In this study, the digital static calibration technique used for 400MSPS, 16-bit high-resolution current steering DAC is described. The calibration technique uses address generator, comparator, SAR register, and calibration DAC to comprise successive approximation calibration loop. With the calibration loop, the respective calibration of array units of(More)
This paper presents a 16-bit 250ksps successive approximation register analog-to-digital converter (SAR-ADC) based on the charge-redistribution technique. The ADC contains a charge-redistribution DAC, a high precision internal voltage reference, a low offset comparator and a serial data interface. The split capacitor array was used to save the area of the(More)
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