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A novel reconfigurable hybrid single electron transis-tor/MOSFET (SETMOS) circuit architecture, namely, reconfigurable pseudo-NMOS-like logic is proposed. Based on the hybrid SETMOS in-verter/buffer circuit cell, reconfigurable pseudo-NMOS-like logics that can work normally at room temperature are constructed. This kind of reconfigurable logic can implement(More)
This paper presents the design and implementation of a high performance sparse matrix-vector multiplication (SpMV) on field-programmable gate array (FPGA). By proposing a new storage format to compress the indexes of non-zero elements by exploiting the sub-structure of the sparse matrix, our SpMV implementation on a recon-figurable computing platform with a(More)
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